The present invention relates to a digital information storage apparatuses such as a magnetic disk driver, an optical disk driving device, and a magnetic tape unit as well as digital information systems including a digital communication apparatus operating, for example, in the asynchronous transfer mode (ATM), and in particular, to a digital information signal data reproducing circuit including a clock control circuit supervising the frequency and phase of clock pulses which determines timing of the sampling of reproduction signals in the digital information system of the above type and to a digital information system employing the digital information signal data reproducing circuit.
Signals read from a storage media in the digital storage apparatuses described above and reception signals received via a transmission route in the digital communication system are generally in an analog form. Consequently, it is necessary to sample the signals in the analog form according to a timing clock signal extracted by timing extraction means so as to transform the analog signals into signals in a digital form. For example, there has been known a representative method of this signal processing, namely, a partial response maximum likelihood (PRML) method for use with a magnetic disk drive. In this method, according to a partial response (PR) signal read from a recording media, there is created a timing clock signal by timing extraction means including a phase locked loop (PLL) circuit such that the partial response signal is sampled to convert the analog signal into a digital signal according to the maximum likelyhood method.
FIG. 23 shows a conventional PRML signal processing circuit employed to reproduce signals in a magnetic disk unit. In operation, a differential reproduction signal read from a magnetic disk 1001 as the recording media and reproduced by a magnetic head 1002 is then amplified by an amplifier 1003, and then a high-frequency component as a noise is removed from the amplified signal by a active filter (AF) 1004. The resultant signal is sampled by an analog-to-digital converter (ADC) 1005 according to timing of a clock signal generated from a clock control circuit 1080 to be transformed into a digital signal. The signal from the converter 1005 is equalized with respect to the waveform by a digital equalizer (DEQ) 1006 and then is decoded by a viterbi decoder 1007 through a maximum likelihood process according to the viterbi decoding algorithm.
In the clock controller 1080, the signals from the digital equalizer 1006 are processed such that a gradient of amplitude values (including the sign) of the signals at two adjacent points is detected as a phase error. According to the phase error, an appropriate current is supplied from a digital-to-analog converter (DAC) 1009 such that the high-frequency component is removed from the signal by a loop filter 1010 to be transformed into a voltage signal. In response to the output voltage from the loop filter 1010, the frequency of a voltage controlled oscillator (VCO) 1011 is controlled to resultantly generate the clock signal. Details about the digital phase comparator have been described in pages 516 to 531 of an article "Timing Recovery in Digital Synchronous Data Receivers", IEEE Transactions On Communications, Vol. COM-24, No. 5 published in May 1976.
The clock controller 1080 includes a digital control loop including the ADC 1005, digital equalizer 1006, digital phase comparator 1008, DAC 1009, loop filter 1010, and VOC 1011 and hence is called a digital phase locked loop (PLL).
FIG. 24 shows a data format used in the magnetic disk unit. Each data includes a synchronizing (sync) data item 1100 including a fixed pattern such as 1,1,-1,-1! and a user data item 1200. According to the reproducing method, while the sync data 1100 is being reproduced, the frequency and phase of the clock control circuit 1080 are adjusted by itself to those of the reproduced signal. When the clock adjustment or capturing is completely finished, the user data 1200 is reproduced. Since the sync data 1100 including about 20 bytes to about 30 bytes is written on the recording media 1001 on which the user data 1200 is also recorded, i.e., the user data recording capacity is also consumed by the sync data 1100.
In the clock control circuit 1080 of FIG. 23 using the conventional digital PLL, when the characteristic frequency (to be referred to as a gain herebelow) is set to a higher value to increase the adjustment of the frequency and phase in which the frequency and phase of the clock signal are to be captured as above, the phase margin is reduced due to a long loop delay of the feed-back control, which possibly leads to a problem of insufficient stability of the system. The gain determines the frequency capture range and time and hence is one of the essential setting parameters associated with the performance of the clock control circuit 1080.
For example, in a case of a digital PLL having a loop delay of 20 clocks, even when the gain is increased to its maximum value, at least 20 bytes are required for the sync data 1100 to capture the frequency deviation of about 0.5%. In other words, the conventional digital data reproducing circuit using the digital PLL is accompanied by drawbacks of a narrow frequency capture range and a long sync capture time. This additionally results in a disadvantage that the sync data is also increased and hence the user data record capacity is accordingly minimized. It has been required in the markets that a frequency deviation of about 3% is captured with a sync data length of 12 bytes or less. This requirement consequently cannot be fully satisfied by the conventional control method using the digital PLL.